Circuit and method for modeling I/O

ABSTRACT

A behavioral modeling technique that captures driver delay. The output characteristics of a typical driver are represented by two basic element types: switching and non-switching. Switching elements are functions of both time-varying and non-time-varying parameters, and non-switching elements are functions of non-time-varying parameters only. The outputs of these elements are characterized and tabulated by applying a DC voltage on the output of the driver and measuring the current through each element. The time-varying switching element are represent by time-controlled resistors. The invention provides a methodology to account for variations in input transition rate, supply voltage(s) or temperature.

[0001] This invention claims prority based on Provisional PatentApplication No. 60/288,813 filed on May 5, 2001.

BACKGROUND OF THE INVENTION

[0002] This invention relates to methods and systems used for generatingbehavioral models used in integrated circuit design. More particularly,the present invention provides for a new behavioral model that providestiming, noise and integrity grid analysis.

[0003] When simulating I/O electrical performance during timingcharacterization, signal integrity analysis, and power grid integrityanalysis, various I/O modeling techniques have been used. At one end ofthe modeling spectrum are the full netlist models that contain detailedarchitectural and parasitic information of the I/O. These models providethe highest level of accuracy and can be used for a variety of analysis.A major disadvantage of full netlist models are excessive simulationtimes that prohibit them from being used at the chip level andnon-convergence under certain conditions. At the other end of thespectrum are empirical models for driver delay and IBIS models forsignal integrity analysis.

[0004] Empirical models use simple equations or lookup tables forpredicting driver delay and output slew rate. The advantage of empiricalmodels is fast simulation time. The disadvantages are poor accuracyunder certain conditions, and they are typically limited to timinganalysis. For signal integrity analysis IBIS models can be used. Theadvantage of these models are accurate driver output waveforms across awide range of loading conditions. The disadvantages are they cannot beused for timing analysis and the models do not predict driversensitivity to variations in supply voltage, temperature, and input slewrate.

[0005] I/O behavioral modeling in the form of IBIS models has gainedwide acceptance in signal integrity analysis. While the IBIS modelaccurately represents the characteristics of the output pin at threefixed process corners, it does not model driver delay or account forvariations in temperature, supply voltages, and input transition rate.The IBIS models used today by various board level simulation tools forsignal integrity analysis are behavioral in nature and offer the userand developer of the models several advantages over full-netlist models.First, because IBIS models are behavioral, they contain no proprietaryinformation. This makes it easy to exchange information about I/Ocharacteristics without disclosing intellectual property. Second,behavioral simulation is faster than full-netlist simulation (e.g.,Spice) because it uses higher-level abstraction models. What would beprohibitive in terms of simulation time when using full-netlist modelscan be accomplished in reasonable time with behavioral models.

[0006] The IBIS specification (ANSI/EIA-656-A, “I/O Buffer InformationSpecification (IBIS) Version 3.2”, September 1999), presents severaltechniques for improving model accuracy across a wide range of I/Ofamily types for signal integrity analysis. I/O behavior modeling (e.g.IBIS I/O Buffer Information Specification) have been used by industry inPCB level signal integrity tools such as SpectraQuest from Cadence andXTK from Viewlogic for several years.

BRIEF SUMMARY OF THE INVENTION

[0007] Unfortunately, the IBIS techniques do not model driver delay,pre-drive currents, or n-well decoupling structures which would berequired for timing, noise, and power grid integrity analysis. Inaddition, no techniques are available to the IBIS model developer toaccount for variations in temperature, supply voltages, and inputtransition rate. This invention provides a new and powerful behaviormodel that overcomes the IBIS limitations and is appropriate for mergeddigital-analog timing, noise, and power grid analysis.

[0008] A new modeling technique provided by this invention preserves theaccuracy of the full netlist model, simulates orders of magnitudefaster, and can be used for timing, power grid integrity, and signalintegrity analysis over a wide range of supply voltage(s), temperature,input slew rate, and loading conditions. Because of the relativesimplicity of this new modeling technique as compared to a full netlistmodel, non-convergence issues at run time are ameliorated.

[0009] Additional advantages of this invention are 1) the behavioralmodel provided here captures driver delay, thereby allowing on-chip andoff-chip timing to be merged into a seamless interface, 2) I/O currentwaveforms are readily available for on-chip power grid integrityanalysis, and 3) signal integrity analysis at the chip level isavailable without the need of procuring othre software. Furthermore, thebehavioral model provided by this invention can be used to enhance otherapplications that currently perform package noise analysis using fullnetlist models which greatly limits the cross sectional size it cananalyze at one time. These advantages enable these models, hereinreferred to as “BIO” (Behavioral I/O) models, to form a seamlessinterface between on-chip and off-chip timing. They can also provideaccurate rail current waveforms for power grid analysis tools and I/Oplacement tools. Because BIO models have the ability to handle groundbounce and power supply collapse, they can also be used in signalintegrity tools.

[0010] In order to accomplish this invention provides a method formodeling the inputs and outputs of integrated circuits, comprising thesteps of representing in the model the output characteristics of drivercircuits by two types of elements, switching and non-switching;tabulating the output characteristics for each of the elements byapplying a DC voltage source on the output of the driver and measuringthe current through each element; representing in the model switchingelements as a voltage-time controlled resistors by obtaining the productof DC impedance as a function of voltage and a scalar that is a functionof time; and embedding in the model equations that are functions ofinput edge arrival times and cycle time for each scalar type.

[0011] The circuit used for modeling comprises switching elementsconnected serially as voltage-time controlled resistors; one of theconductive elements acts to pull voltage up, while the other conductiveelements acts to pulls the voltage down; and non-switching elementsconnected serially as resistors, one representing power structures andthe other representing ground clamping structures; each of the switchingelements is tied to input stage and both the switching and non-switchingelements is tied to an output.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 illustrates an example driver structure used to illustratethe characterization techniques of both switching and non-switchingelements.

[0013]FIG. 2a illustrates waveforms for characterizing the NFET turn-oncharacteristics of a driver.

[0014]FIG. 2b illustrates characterization of the nfet turn-on and pfetturn-off rates.

[0015]FIG. 2c illustrates the characterization of the pfet turn-on andnfet turn-off rates represented as scalars values as a function of time.

[0016]FIG. 3 illustrates sensitivity to variable parameters such astemperature for a NFET turn-on scalar.

[0017]FIG. 4a illustrates how the DC conductance is obtained.

[0018]FIG. 4b illustrates how the transient conductance of a device isobtained.

[0019]FIG. 4c illustrates the transient conductance of a device.

[0020]FIG. 5a illustrates the determination scalar values as a functionof time at some fixed voltage and temperature denoted by Env1.

[0021]FIG. 5b illustrates how the scalars values from FIG. 5b arerepresented in tabular format within the BIO model.

[0022]FIG. 5c is simple illustration of how these scalar values mightchange due to variations in voltage, temperature, and input slew ratedenoted by Env2.

[0023]FIG. 6 illustrates the behavioral model topology provided by thisinvention.

[0024]FIG. 7 illustrates a static timer using the BIO model of thisinvention.

[0025]FIG. 8 illustrates the use of the BIO model in the mixed signalenvironment.

[0026]FIG. 9 illustrates a typical hardware configuration of aninformation handling/computer system for modeling. integrated circuitsin accordance with the invention.

[0027]FIG. 10 illustrates an example of signal bearing media.

[0028]FIG. 11 illustrates a characterization of the decoupling stage ofthe model topology of FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

[0029] The output characteristics of a typical driver are represented bytwo basic element types: switching and non-switching. Switching elementsare functions of both time-varying and non-time-varying parameters, andnon-switching elements are functions of non-time-varying parametersonly. Examples of switching elements are nfets and pfets. Typically, aswitching element is used to represent the composite transient impedance(conductance) behavior of a pull-up or pull-down network that arecomprised of multiple FETs and parasitics. Examples of non-switchingelements are resistive termination's and ESD structures. ESD impedance(conductance) is essentially a function of device voltage only and cantherefore can be treated as a non-switching element. There are, however,ESD structures that can be dynamically switched that would require aswitching element to represent its impedance.

[0030]FIG. 1 illustrates an example driver structure used to illustratethe characterization techniques of both switching and non-switchingelements. These techniques can easily be extended to other I/Ostructures containing devices that can be classified as either switchingor non-switching.

[0031] The first step is to characterize the dc impedance for eachelement in FIG. 1 at a fixed temperature and supply voltage. Thisimpedance, which we call the dc_base impedance, is tabulated as afunction of device voltage. To account for variations in temperature andsupply voltages, device impedance can be obtained from the dc_baseaccording to equation (1) below.

dc _(—) impedance=(1+D0)*dc _(—) base  (1)

[0032] The value for D0 is calculated prior to simulation time using anempirical equation which is a function of both temperature and supplyvoltage. The sensitivity this parameter has to device voltage is small,allowing the use of a simple scalar technique across the full range ofdc_base impedance values.

[0033] For each element type, it's dc impedance as a function of thevoltage across it is tabulated as shown in Table 1 below: TABLE 1 TABLEDC POWER CLAMP TABLE DC GROUND CLAMP Vpowerclamp Resistance VgroundclampResistance 0 10000 0 10000 0.7 100 0.7 100 5 1 5 1 TABLE DC PFET TABLEDC NFET Vpfet Resistance Vnfet Resistance 10 40 5 40 5 42 0 42 0 43 −543

[0034] In addition to dc impedance, for each switching type of element,the turn-on and turn-off rates are characterized by observing thetransient impedance during rising and falling output waveforms.

[0035]FIG. 2a illustrates waveforms for characterizing the NFET turn-oncharacteristics of a driver. The transient impedance of the NFET turningon is a function of device voltage and of “local time”, that begins atthe midpoint of the input transition. Normalizing the transientimpedance to the dc impedance (function of device voltage) produces atime-varying scalar representing the turn-on rate of the NFET,independent of the load that was used during characterization. Thisscalar is unity when the NFET is completely turned on, and very largewhen the NFET is off. For this same transition and same “local time”,another time-varying scalar is obtained for the PFET turn-off.Similarly, a different “local time” for the output-rising transition isused as the basis for PFET turn-on and NFET turn-off scalars. Thiscollection of four scalars is saved in tabular format. FIG. 2billustrates characterization of the nfet turn-on and pfet turn-offrates. FIG. 2c illustrates the characterization of the pfet turn-on andnfet turn-off rates represented as scalar values as a function of time.

[0036] In order to enable behavioral simulation of periodic waveforms,the “local times” are made periodic through their definitions asfunctions of periodic rising and falling input edge arrival times. Thetime indexing of each scalar is unique. For example, the zero timereference for the nfet_on and pfet_off scalars corresponds to the time afalling input wave crosses it's midpoint while the nfet_off and pfet_onscalars correspond to a rising input wave. The four equations below, onefor each scalar type, control the time indexing of the scalars.

pfet _(—) on _(—) time=mod((time+period−fall),period)−((period*(1−edge))+rise−fall)

pfet _(—) off _(—) time=mod((time+period−fall), period)

nfet _(—) on _(—) time=mod((time+period−rise),period)−((period*edge)−rise+fall)

nfet _(—) off _(—) time=mod((time+period−rise), period)

[0037] where

[0038] time=simulation time parameter

[0039] period=time per cycle

[0040] rise=rising input edge arrival time

[0041] fall=falling input edge arrival time

[0042] edge=0 if fall>rise and 1 if rise>fall

[0043] Other timing schemes can be used. They will likely have bothadvantages and disadvantages over the equations enumerated above.

[0044] While the “local times” are now periodic, they do not yet accountfor variations in input transition rate, supply voltage(s), ortemperature. Sensitivity to these parameters is illustrated in FIG. 3for the NFET turn-on scalar. The waveform NFET turn-on base representsthe NFET turn-on scalar as generated at the base input transition rate,supply voltage(s), and temperature. As these parameters vary, the scalarfurther varies as the waveform NFET turn-on; only the time scale ischanging, because the scalar is already normalized to its' dc impedance.This time scale change is implemented by defining a “modified localtime” with a piece wise-linear monotonic relationship to the originallocal time. The “modified local time” has a delay K7 and a change inslope K8, with parameter K9 initiating the slope change. The K7 throughK9 parameters are defined from the timing points in FIG. 3 according tothe equations (2) below:

K7=T2−T0

K8=[(T3−T2)−(T1−T0)]/(T1−T0)

K9=T2  (2)

[0045] We next use K7-K9 to define “modified local time” as in theequation (3) below.

NFET _(—) on _(—) time _(—) mod=NFET _(—) on _(—) time+K7++K8*[max(NFET_(—) on _(—) time−K9, 0)]  (3)

[0046] When (NFET_on_time>K2)→Adjust slope according to K1

[0047] Else→No adjustment to slope

[0048] Like the D0 parameter in equation (1), values for K7, K8, and K9are calculated prior to run time using empirical equations which arefunctions of temperature, supply voltages, and input transition rateobtained from actual parameter values. If conditions at run time are thesame as those used to generate the nfet turn-on base waveform in FIG. 3,then K7 and K8 are set to zero; otherwise, they are set to non-zerovalues to appropriately modify the time sequence parameter. The turn-onimpedance of the NFET can now be represented as the product of thescalar (in this case the NFET turn-on scalar) which varies with“modified local time” and the NFET dc impedance.

[0049] To account for all these variations in each scalar, the scalarindexing equations listed above are modulated using the K1-K12 termsbelow as a function of supply voltage(s), temperature, and input slewrate.

pfet _(—) on _(—) time _(—) mod=pfet _(—) on _(—) time+(K1+K2*(pfet _(—)on _(—) time−K3))

pfet _(—) off _(—) time _(—) mod=pfet _(—) off _(—) time+(K4+K5*(pfet_(—) off _(—) time−K6))

nfet _(—) on _(—) time _(—) mod=nfet _(—) on _(—) time+(K7+K8*(nfet _(—)on _(—) time−K9))

nfet _(—) on _(—) time _(—) mod=nfet _(—) off _(—) time+(K10+K11*(nfet_(—) off _(—) time−K12))

[0050] Where Kxx=f{voltage, temperature, and input slew}

[0051] To account for dc fet impedance sensitivity to temperature andsupply voltage changes, the dc impedance for each element in FIG. 2 ismodulated using the K13-K16 terms below as a function of voltage andtemperature.

power _(—) clamp _(—) dc _(—) mod=power _(—) clamp _(—) dc*(1+K13)

ground _(—) clamp _(—) dc _(—) mod=groung _(—) clamp _(—) dc*(1+K14)

pfet _(—) dc _(—) mod=pfet _(—) dc*(1+K15)

nfet _(—) dc _(—) mod=nfet _(—) dc*(1+K16)

[0052] The nfet and pfet impedance is given as

Rpfet=[pfet _(—) dc _(—) mod]*[pfet _(—) on _(—) scalar]||[pfet _(—) dc_(—) mod]*[pfet _(—) off _(—) scalar]

Rnfet=[nfet _(—) dc _(—) mod]*[nfet _(—) on _(—) scalar]||[nfet _(—) dc_(—) mod]*[pfet _(—) off _(—) scalar]

[0053] where

[0054] pfet_on_scalar=f{pfet_on_time_mod}

[0055] nfet_on_scalar=f{nfet_on_time_mod}

[0056] pfet_off_scalar=f{pfet_off_time_mod}

[0057] nfet_off_scalar=f{nfet_off_time_mod}

[0058] The power and ground clamp impedance is given as

Rpwrclamp=power_clamp_dc_mod

Rgndclamp=ground_clamp_dc_mod

[0059] Again it should be emphasized that the use of PFETs and NFETS isjust illustrative. The model can be used with any switching element thatpulls up or pulls down voltage.

[0060] Alternatively, the model can use conductance versus impedancewhen creating the model. FIGS. 4a, 4 b, and 4 c illustrate this. Exampleof variable conductance as a function of device voltage and time.

[0061]FIG. 4a illustrates how the DC conductance of a device isobtained. The DC conductance of a device (e.g. Pullup or Pulldown) ischaracterized as a function of device voltage. For this example, theconductance varies from 10-35 over a device voltage range of 0-3 volts.

[0062]FIG. 4b illustrates how the transient conductance of a device isobtained. To capture the transient conductance of the device, the DCconductance of the device is multiplied by a scalar that is a functionof time. For this example the scalar ranges from 1, corresponding towhen the device is turned on, to 0 when the device is turned-off. Thescalar represents the rate at which the device turns off.

[0063]FIG. 4c illustrates the transient conductance of a device. Thetransient conductance of the device is shown to vary from 35,corresponding to when the device is on, to 0 when the device is off.Note that the transient conductance is a function of both device voltageand time. Note that time is referenced to the midpoint of the inputsignal. This synchronizes the input and output waveforms of the BIOmodel.

[0064] A simple example to illustrate the concept of a BIO modeladjustment parameter based on conductance scalars and how it is handledwithin the BIO model is presented in FIGS. 5a, 5 b and c. FIG. 5aillustrates the determination scalar values as a function of time atsome fixed voltage and temperature denoted by Env1. FIG. 5b illustrateshow the scalars values from FIG. 5b are represented in tabular formatwithin the BIO model. FIG. 5c is simple illustration of how these scalarvalues might change due to variations in voltage, temperature, and inputslew rate denoted by Env2.

[0065] The goal is to be able to use the scalar table (Scalar@Env1)within the BIO model to accurately reproduce the scalar values at Env2.To do this, we introduce a time shift parameter K0 such that . . .

[0066] Scalar@Env2(Time)=Scalar@Env1(Time−K0) where K0=1 for thisexample

[0067] K0=f{voltage, temperature, input slew rate}

[0068] With the appropriate value for K0 calculated prior to simulation,the scalar table within the BIO model can be adjusted for any time shiftdue to changes in voltage, temperature, and input slew rate.

[0069]FIG. 6 illustrates the behavioral model topology. The output drivestage consists of resistances which are functions of input edge arrivaltimes, input transition rate, supply voltage(s), device voltage, andtemperature representing the NFET and PFET as described above. The ESDstage contains resistances representing the power and ground ESDstructures which are functions of supply voltage(s), device voltage, andtemperature.

[0070] While the output drive and ESD clamp stages contain thebehavioral characteristics necessary for timing and signal integrityanalysis, the pre-drive current and decoupling stages contain additionalbehavioral characteristics necessary for noise and power grid integrityanalysis. Each device within these stages can be represented by either afixed-value element, a non-switching element that is a function ofparameters not varying in time, or a switching element which is afunction of both time and non-time varying parameters. A tradeoffbetween model complexity and accuracy typically defines the type ofelement used.

[0071] There are many characterization techniques that we have developedfor generating the data that describes the elements of the model. TheI/O family type determines the appropriate techniques to use. Note thatthis only affects the data values that go into the model, not the modeltopology or algorithms. FIG. 11 illustrates one of the characterizationtechniques used for the decoupling stage. The method for characterizingthe decoupling structure of FIG. 11 involves the following steps:

[0072] 1) Switch S1 is closed at t_(o) and charges node A to V_(cc).

[0073] 2) Switch S1 is open before t₁.

[0074] 3) Switch S2 is closed at t₁.

[0075] 4) From the waveform:

Cnear=(V2*Cext)/(V _(cc) −V1)

Cfar=(V2*(Cnear=Cext)−V _(cc) *Cnear)/(V _(cc) −V2)

[0076] R_(pi) is calculated from the RC time constant associated withthe waveform going from V1 to V2 where

C=Cext+Cfar+Cnear and R=R _(pi).

[0077] The I/O family type is also used to characterize the predrivestage. For this characterization, the supply current minus the outputstage current is used to define the resistance (conductance) of thepredrive in the equation as follows:

R1(t)=Vcc1/Icc1 and R2(t)=Vcc2/(Icc2−output stage current)

[0078] R1 and R2 are then recorded in tabular format within the model.

[0079] Typically there is good output waveform correlation among the“BIO” model of FIG. 6, IBIS models and full netlist models. Modelaccuracy begins to diverge after a change in voltage Vcc1 to thepre-drive circuits, temperature, and input transition rate. While theBIO model and full netlist models track across a wide range ofconditions, the IBIS model is unable to adjust for varying conditions.When the output supply voltage Vcc2 is also allowed to change, IBISmodel inaccuracies typically increase further. The high level ofcorrelation between the BIO model and the full-netlist model permits BIOmodels use in both timing and signal integrity analysis. For a given I/Othe same BIO model can be used across a wide range of conditions forsignal integrity analysis, unlike an IBIS model that is only valid at afixed voltage, temperature, and input slew rate. This, together with theBIO model's ability to capture driver delay and power grid currentwaveforms, makes BIO models much more versatile and suitable for an ASICenvironment.

[0080] The equation overhead and six resistive element BIO model (2static elements, 2 pfet elements, and 2 nfet elements) shown in FIG. 6exhibit outstanding accuracy across a wide range of voltage,temperature, input slew rate, and off-chip net conditions and has beendemonstrated across a wide range of I/O family types (e.g. CMOS, PECL,LVDS, GTL, etc,.) In addition whether being used for timing, noise, orsignal integrity analysis, the BIO model's simulation times aretypically less than 1% of the simulation time required for full-netlistmodels. The difference in simulation time becomes even more pronouncedfor increasingly complex I/O's. The reason is because the complexity ofthe behavioral model remains essentially constant as the complexity orsize of the full netlist model increases. This makes possible a mergerof analog and digital simulation techniques at the chip level.

[0081] Using the behavioral model of FIG. 6, the static timer can mergeon-chip and off-chip timing, perform signal integrity and perform I/Opower grid integrity analysis as illustrated in FIG. 7. The scope ofinternal chip static timing has historically ended at thesilicon-package boundary. At this boundary various techniques have beenused to manually interface internal chip timing with off-chip timingthat trade accuracy with simulation run time. The most accuratetechnique is to use a static timer to determine edge arrival times atthe input of the driver and then in a separate spice run that uses fullspice netlist representations of the driver and off-chip net, determinedelay from the input of the driver to the sink end of the net. Theadvantages of this approach are accurate off chip timing and the abilityto perform signal integrity analysis. The disadvantages are 1) excessiverun times when simulating full spice netlist I/O models that prohibitthis technique from being applied at the chip level timing, 2) manualeffort is required to merge on-chip timing with off-chip timing, and 3)many customers do not have the required software licenses for simulatingencrypted spice models.

[0082] A technique that trades accuracy for faster run time is tocalculate a lumped load capacitance that represents the effectivecapacitance as seen by the driver and use this lumped load in anempirical timing model such as a NDR (New Delay Rule) for calculatingdriver delay during static timing. A spice run is then required tocalculate off-chip net delay from the output of the driver to the sinkend of the net. The advantages of this approach are fast run time andreasonable driver delay accuracy assuming the effective capacitance wascalculated correctly. The disadvantages of this approach are 1) theactual shape of the waveform at the output of the driver is notcaptured, therefore the input stimulus used during spice simulation ofthe network is incorrect and will affect accuracy, 2) this techniquedoes not support signal integrity analysis, and 3) manual effort isrequired to merge on-chip and off-chip timing.

[0083] This invention provides one with the ability to embed spicebehavioral models within a static timer such as EinsTimer licensed byIBM or other industry available static timers like PrimeTime by Synopsysand BuildGates by Cadence that preserve the accuracy of a full netlistmodel, run orders of magnitude faster, and gives the static timer theability to do signal integrity and I/O power grid analysis with theaccuracy of spice at the chip level. A static timer is used to time theinternal logic up to the input of the driver in order to determine boththe edge arrival time and slew rate to the driver. A spice deck builderwithin the static timer is used to build a spice deck that referencesboth the driver's spice behavioral model and the spice netlistrepresenting all parasitic and transmission line characteristics fromthe output of the driver to the sink end of the net. User definedmeasurement criteria such as voltages thresholds for delay measurements,frequency, number of cycles, and waveform observation points would beinput to the deck builder that would control delay measurement andsignal integrity analysis. Using the spice deck and the information ofedge arrival time and slew rate to the driver, the static timer theninvokes spice (e.g. PowerSpice) and simulates the entire net in a smallfraction of the time as compared to simulating the entire net using fullspice netlist I/O models. The spice run results are merged with statictiming assertions by the static timer to form a seamless timinginterface between on-chip and off-chip timing.

[0084]FIG. 7 illustrates how such a static timer can be combined withthe BIO models to produce these results. Primary input (PI) assertionsare used to define edge arrival time and slew rate at the input pins ofthe chip. The static timer uses the PI assertions (100), a chip levelcell netlist, and on-chip parasitic information to perform a customarystatic timing analysis (102). The results of this analysis are availablein the internal timing reports (107) that describes all path timinginternal to the chip. Measurement criteria for off-chip timing andsignal integrity analysis are defined (101) and used as input to thespice deck builder (103) within the static timer. The spice deck buildercreates a spice deck (104) that references the off-chip spice netlist(105) and I/O behavioral model (106). Using the spice deck and driverinput assertions from (102), the static timer invokes spice to simulatethe off-chip net. From the spice simulation results, the static timerproduces off-chip timing reports (108) for delay analysis, off-chipvoltage waveforms (109) for signal integrity analysis, and I/O powergrid integrity reports (110) using the current waveforms from the spicesimulations and cell level decoupling information in the NDRs.

[0085] This invention also provides a mixed signal simulationenvironment using the BIO models. FIG. 8 illustrates the use of the BIOmodel in the mixed signal domain. The mixed signal simulation back planeconsists of three basic components; a digital simulation domain 20, forexample an NDR rule containing empirical equations for calculating gatedelay, an analog simulation domain such as a SPICE or PowerSPICEsimulation engine 30, and a control module 10 that merges the twosimulation domains during analysis. All three elements are typicallycoded within the same software language environment (e.g., DCL (“DelayCalculator Language”)) that allows the simulation back plane to beported across multiple operating systems such as RS6000 AIX, Solaris,HP, and Linux. By definition of a back plane, this mixed signalsimulation capability can be exploited by multiple applications. Oneexample is accurate on-chip/off-chip timing within a static timer likethat shown above using BIO models.

[0086] Step 1 is to determine I/O driver delay. To accurately determineI/O driver delay, a static timer such as EinsTimer licensed by IBM orother industry available static timers like PrimeTime by Synopsys andBuildGates by Cadence passes the simulation conditions to the controlmodule 10. These conditions specify the level of modeling required toget the desired level of accuracy. The basic choices are 1) analog suchas full device SPICE net list models, 2) combination of analog-digitalsuch as BIO models, and 3) digital such as NDRs. For this exampleanalog-digital simulation techniques are chosen as the optimal balancebetween simulation speed and accuracy. The simulation conditions alsospecify the rail voltages, temperature, process corner, input-outputedge pair, and input slew rate to the driver.

[0087] Step 2 is to supply a SPICE deck. If a SPICE simulation deck 60does not exist, the control module 10 builds one using the appropriateBIO model 40 and output load 50. The output load describes all silicon,package, and board level parasitics the driver will see.

[0088] In Step 3 the control module 10 passes the environmentalconditions in the parameter library 20. The environmental conditionsbeing obtained from the simulation condition in the control module.

[0089] In Step 4 the parameter library 20 passes BIO model adjustmentparameters back to the control module 10 based on the environmentalconditions.

[0090] In Step 5 the control module (1) passes the adjustmentparameters, environment conditions, BIO Parameter and SPICE deck (6)into the SPICE simulation engine (3). Note at this step the analogcharacteristics of the BIO model have been dynamically adjusted usingdigital simulation techniques prior to analog simulation

[0091] The final step, Step 6, is the spice SPICE simulation. Resultsare then passed back to EinsTimer to be included in static timingreports.

[0092] Another application that this mixed-signal simulation provides isthe ability for greater accuracy on critical paths. Critical paths couldbe determined automatically from slack reports or manually via userinput. Circuit partitioning for leveraging various simulation engines ina seamless interface is a natural attribute for this system.

[0093] Furthermore, the present invention may be implemented in aninformation handling/computer system. For example, FIG. 9 illustrates atypical hardware configuration of an information handling/computersystem for modeling integrated circuits in accordance with theinvention.

[0094] As shown in FIG. 9, the inventive information handling/computersystem (400) preferably has at least one processor or central processingunit (CPU) 411. The CPUs 411 are interconnected via a system bus 412 toa random access memory (RAM) 414, read-only memory (ROM) 416,input/output (I/O) adapter 418 (for connecting peripheral devices suchas disk units 421 and tape drives 440 to the bus 412), user interfaceadapter 422 (for connecting a keyboard 424, mouse 426, speaker 428,microphone 432, and/or other user interface device to the bus 412), acommunication adapter 434 for connecting an information handling systemto a data processing network, the Internet, an Intranet, a personal areanetwork (PAN), etc., and a display adapter 436 for connecting the bus412 to a display device 438 and/or printer 439 (e.g., a digital printeror the like).

[0095] In addition to the hardware/software environment described above,a different aspect of the invention includes a computer-implementedmethod for performing the above method. As an example, this method maybe implemented in the particular environment discussed above.

[0096] Such a method may be implemented, for example, by operating acomputer, as embodied by a digital data processing apparatus, to executea sequence of machine-readable instructions. These instructions mayreside in various types of signal-bearing media.

[0097] Thus, this aspect of the present invention is directed to aprogrammed product, comprising signal-bearing media tangibly embodying aprogram of machine-readable instructions executable by a digital dataprocessor incorporating the CPU 411 and hardware above, to perform themethod of the invention.

[0098] This signal-bearing media may include, for example, a RAMcontained within the CPU 411, as represented by the fast-access storagefor example. Alternatively, the instructions may be contained in anothersignal-bearing media, such as a magnetic data storage diskette 500 (FIG.10), directly or indirectly accessible by the CPU 411.

[0099] Whether contained in the diskette 500, the computer/CPU 411, orelsewhere, the instructions may be stored on a variety ofmachine-readable data storage media, such as DASD storage (e.g., aconventional “hard drive” or a RAID array), magnetic tape, electronicread-only memory (e.g., ROM, EPROM, or EEPROM), an optical storagedevice (e.g. CD-ROM, WORM, DVD, digital optical tape, etc.), paper“punch” cards, or other suitable signal-bearing media includingtransmission media such as digital and analog and communication linksand wireless. In an illustrative embodiment of the invention, themachine-readable instructions may comprise software object code,compiled from a language such as “C”, etc.

[0100] While the invention has been described in terms of specificembodiments, it is evident in view of the foregoing description thatnumberous alternatives, modifications and variations will be apparent tothose skilled in the art. Thus, the invention is intended to encompassall such alternatives, modifications and variations which fall withinthe scope and spirit of the invention and the appended claims.

What is claimed is:
 1. A method for modeling the inputs and outputsintegrated circuits, comprising the steps of: representing in the modelthe output characteristics of driver circuits by two types of elementsswitching and non-switching; tabulating the output characteristics foreach of the elements by applying a DC voltage source on the output ofthe driver and measuring the current through each element; representingin the model switching elements as a voltage-time controlled resistorsby obtaining the product of DC impedance as a function of voltage and ascalar that is a function of time; and embedding in the model equationsthat are functions of input edge arrival times and cycle time for eachscalar type.
 2. The method of claim 1 also comprising the step of:accounting for variations in temperature and supply voltages, device DCcharacteristic can be obtained from the dc_base according to theequation: dc_impedance=(1+D0)*dc_base, where DO is a function of supplyvoltage and temperature
 3. The method of claim 1 where the step ofrepresenting as a voltage time controlled resistor also comprises thestep of: normalizing the time controlled impedance to the dc impedanceto produce a time-varying scalar independent of the load used duringcharacterization.
 4. The method of claim 1 where such representation ofthe voltage-time controlled resistor is obtained starting with amidpoint of the input transition.
 5. The method of claim 1 alsocomprising the step of saving the scalars in a tabular format.
 6. Themethod of claim 1 also comprising the step of making wave-forms for theswitching elements periodic in definitions as functions of periodicrising and falling input edge arrival times.
 7. The method of claim 1also comprising the step of applying indexing equations to account forvariations in environmental conditions.
 8. The method of claim 7 whereinthe environmental conditions are slew rate, temperature or supplyvoltage.
 9. The method of claim 1 where the switching elements reflectcomposite transient impedance behavior of a pull-up or pull-down networkthat are comprised of a plurality of FETs and parasitics.
 10. The methodof claim 1 where the non-switching elements are an ESD device and apower clamp.
 11. The method of claim 1 where the method also comprisingthe steps of obtaining behavioral characteristics for a pre-drivecurrent stage and a decoupling stage and applying them to the model. 12.A method for modeling the inputs and outputs integrated circuits,comprising the steps of: representing in the model the outputcharacteristics of driver circuits by two types of elements, switchingand non-switching; tabulating the output characteristics for each of theelements by applying a DC voltage source on the output of the driver andmeasuring the current through each element; representing in the modelswitching elements as a voltage-time controlled resistors by obtainingthe product of DC conductance as a function of voltage and a scalar thatis a function of time; and embedding in the model equations that arefunctions of input edge arrival times and cycle time for each scalartype.
 13. The method of claim 12 also comprising the step of: accountingfor variations in temperature and supply voltages, device characteristiccan be obtained from the dc_base according to the equation:dc_conductance=(1+D0)*dc_base, where DO is a function of supply voltageand temperature
 14. The method of claim 12 where the step ofrepresenting as a voltage time controlled resistor also comprises thestep of: normalizing the time controlled conductance to the dcconductance to produce a time-varying scalar independent of the loadused during characterization.
 15. The method of claim 12 where suchrepresentation of the voltage-time controlled resistor is obtainedstarting with a midpoint of the input transition.
 16. The method ofclaim 12 also comprising the step of saving the scalars in a tabularformat.
 17. The method of claim 12 also comprising the step of makingwave-forms for the switching elements periodic in definitions asfunctions of periodic rising and falling input edge arrival times. 18.The method of claim 12 also comprising the step of applying indexingequations to account for variations in environmental conditions.
 19. Themethod of claim 18 wherein the environmental conditions are slew rate,temperature or supply voltage.
 20. The method of claim 12 where theswitching elements reflect composite transient conductance behavior of apull-up or pull-down network that are comprised of a plurality of FETsand parasitics
 21. The method of claim 12 where the non-switchingelements are an ESD device and a power clamp.
 22. The method of claim 12where the method also comprising the steps of obtaining behavioralcharacteristics for a pre-drive current stage and a decoupling stage andapplying them to the model.
 23. A circuit which is used to modelintegrated circuits which comprises: switching elements connectedserially as voltage-time controlled resistors, one of the conductiveelements acts to pull voltage up, the other conductive elements acts topulls the voltage down; and non-switching elements connected serially asresistors, one representing power structures and the other representingground clamping structures; each of the switching elements tied to inputstage and both the switching and non-switching elements tied to anoutput
 24. The circuit of claim 23 which also comprises a pre-drivestage coupled to the switching elements and a decoupling stage tied tothe switching and non-switching elements and the pre-drive stage. 25.The circuit of claim 24 where a fixed value element is used to representthe pre-drive or decoupling stage.
 26. The circuit of claim 24 where anon-switching element that is a function of parameters that not vary intime is used to represent the pre-drive or decoupling stage.
 27. Thecircuit of claim 24 where a switching element which is a function ofboth time and non-time varying parameters is used to represent thepre-drive or decoupling stage.
 28. A method for modeling the inputs andoutputs integrated circuits, comprising the steps of: representing inthe model the output characteristics of driver circuits by two types ofelements, switching and non-switching; tabulating the outputcharacteristics for each of the elements by applying a DC voltage sourceon the output of the driver and measuring the current through eachelement; representing in the model switching elements as a voltage-timecontrolled resistors by obtaining the product of DC conductance orimpedance as a function of voltage and a scalar that is a function oftime; accounting for variations in input slew rate, temperature, andsupply voltages where device turn-on characteristic can be obtained fromdevice_turn_on_base according to the equation:device_turn_on=device_turn_on_base+(K0+K1*max (device_turn_on_base−K2,0)), where K0, K1, and K2 are functions of supply voltage, input slewrate, and temperature; accounting for variations in temperature andsupply voltages, device DC characteristic can be obtained from thedc_base according to the equation: dc_impedance(conductance)=(1+D0)*dc_base, where DO is a function of supply voltageand temperature; and embedding in the model equations that are functionsof input edge arrival times and cycle time for each scalar type.
 29. Amethod for modeling the inputs and outputs integrated circuits,comprising the steps of: representing in the model the outputcharacteristics of driver circuits by two types of elements, switchingand non-switching; tabulating the output characteristics for each of theelements by applying a DC voltage source on the output of the driver andmeasuring the current through each element; representing in the modelswitching elements as a voltage-time controlled resistors by obtainingthe product of DC conductance or impedance as a function of voltage anda scalar that is a function of time; accounting for variations in inputslew rate, temperature, and supply voltages, device turn-oncharacteristic can be obtained from device_turn_on_base according to theequation: device_turn_on=device_turn_on_base+(K0+K1*max(device_turn_on_base−K2, 0)), where K0, K1, and K2 are functions ofsupply voltage, input slew rate, and temperature; accounting forvariations in temperature and supply voltages, device DC characteristiccan be obtained from the dc_base according to the equation:dc_impedance(conductance)=(1+D0)*dc_base, where DO is a function ofsupply voltage and temperature; and embedding in the model equationsthat are functions of input edge arrival times and cycle time for eachscalar type.